The present invention relates, in general, to the field of integrated circuit memory devices and devices incorporating embedded memory arrays. More particularly, the present invention relates to a clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM.
It has long been a goal of memory design to increase the performance of DRAM in order to support higher speed processors. One method of increasing DRAM performance is to increase the “read” and “write” data rate across the memory bus. SDRAM access times and burst data rates are constantly improving by manufacturing process “shrinks” and improved interconnect technology. Additionally, improved command bus utilization has been achieved by reducing the number of instructions needed to perform certain memory operations. In general, the fewer command cycles which are required for the execution of memory commands results in more bus cycles which are then available for memory data transfers.
To date, several approaches have been used to minimize the number of command cycles needed to access SDRAM devices and embedded arrays. One example is the use of “burst accesses” which utilize a single “read” or “write” command execution in order to read or write to multiple sequential words. Another technique for reducing the number of command cycles required to access SDRAMs is the use of an “auto-precharge” mode of operation. Auto-precharge is a programmable mode wherein a “precharge” operation automatically occurs at the end of a predetermined number of burst “read” or “write” cycles without requiring the assertion of an external “precharge” command. Similarly, the execution of a “refresh” command in SDRAMs results in the device automatically precharging at the end of the “refresh” operation.
U.S. Pat. No. 6,288,959 issued on Sep. 11, 2001 entitled “Controlling the Precharge Operation in a DRAM Array in a SRAM Interface” describes a technique wherein the precharge operation of a DRAM array in a non-multiplexed address interface is controlled so that the DRAM is precharged only if there is a change in the word line address in order to effectuate a power saving. However, the technique described employs an activity monitor circuit in series with the address path which appreciably slows down memory accesses. Moreover, the memory arrays can remain active for relatively long periods of time thereby dissipating leakage power.
U.S. Pat. No. 6,510,091 issued on Jan. 21, 2003 entitled “Dynamic Precharge Decode Scheme for Fast DRAM” describes a DRAM which includes first and second address generators, subarrays, an address decode path and a precharge activation path wherein the precharge activation path and the address decode path are matched and wherein the occurrence of an event during an active phase, for example a sense amplifier set signal initiation, initiates the precharge phase process. Through use of the technique described, address pre-decoding and precharging may be performed simultaneously, but the precharge operation starts at the end of the cycle.
Other approaches are described, for example, in U.S. Pat. No. 5,963,497 issued Oct. 5, 1999 for “Dynamic Random Access Memory System with Simultaneous Access and Refresh Operations and Method for Using the Same” and U.S. Pat. No. 6,222,786 issued Apr. 24, 2001 for “Dynamic Random Access Memory with Write-Without-Restore and Systems and Methods Using the Same”.